This invention relates generally to floating gate memory devices such as an array of flash electrically, erasable programmable read-only memory (EEPROM) cells. More particularly, the present invention relates to a unified program method and circuitry used in an array of Flash EEPROM memory cells for concurrently programming and verifying the programmable threshold voltage levels in the selected memory cells during programming which is simple in its construction and consumes less power than has been traditionally available.
As is generally well-known in the art, there have been provided electrical programmable and erasable memory array devices using a floating gate for the storage of charges thereon which are sometimes referred to as "Flash EPROMs or EEPROMs". In such conventional EEPROM memory device, a plurality of one-transistor core cells may be formed on a semiconductor substrate in which each cell is comprised of a P-type conductivity substrate, an N-type conductivity source region formed integrally with the substrate, and an N-type conductivity drain region also formed integrally within the substrate. A floating gate is separated from the substrate by a thin dielectric layer. A second dielectric layer separates a control gate from the floating gate. A P-type channel region in the substrate separates the source and drain regions.
Such EEPROMs are programmed in a conventional operation via hot-electron injection to the floating gate by application of high voltages to the control gate and the drain region which are above the potential applied to the source region. For example, the drain voltage applied is approximately +5.5 volts and the control gate voltage is approximately +12 volts. The source region is held at a ground potential. For the erasing operation by way of Fowler-Norheim tunneling, a positive voltage (e.g., +5 volts) is applied to the source region. A negative voltage (e.g., -8 volts) is applied to the control gate, and the drain region is allowed to float. In a read operation, the source region is held at a ground potential (0 volts) and the control gate has applied thereto a voltage of about +5 volts. The drain region is held at a voltage between +1 to +2 volts. Under these conditions, an unprogrammed or erased cell (storing a logic "1") will conduct a predetermined amount of current. On the other hand, the programmed cell (storing a logic "0") will not be rendered conductive. It should be clearly understood that the above examples are given for explanation only and that other voltage values may be used so as to provide similar programming, erasing, and reading operations.
In particular, there is known in the prior art of one conventional programming technique which applies a plurality of pulses in order to program a memory cell in a Flash EEPROM array from a logic state "1" to a logic state "0". After each programming pulse, a program verify operation is performed so as to read the state programmed in order to verify if the desired state has been achieved. Since bias conditions for the respective programming operation and program verify operation are quite different, this prior art programming technique suffers from the disadvantage of requiring additional time for switching between the two bias conditions. Further, if more than one programming pulse is required for programming the cell, there will be a substantial amount of time used for the non-programming operations. Another drawback encountered by the programming pulse technique is due to the fact that the actual programming time is discrete since it is determined by the total number of pulses applied. In addition, there will be a problem of over-programming associated with this programming technique if there is an upper limit for the programmed threshold voltage.
In an attempt to solve the problems discussed above with the programming pulse technique, there has been also provided heretofore in the prior art of a programming method for Flash EEPROM memory cells which combines the programming mode of operation with the program verify mode of operation into one step. Such a program method is described and illustrated in U.S. Pat. No. 5,712,815 to C. S. Bill et al. entitled "Multiple Bits Per-Cell Flash EEPROM Capable of Concurrently Programming and Verifying Memory Cells and Reference Cells," which is hereby incorporated by reference in its entirety.
This '815 patent is based upon a different hot carrier injection mechanism, i.e., drain-side injection at low drain current levels, than the conventional channel hot-carrier injection mechanism used in most Flash EEPROM memory devices. Thus, the program method in the '815 patent suffers from the disadvantage of requiring special circuit elements so as to accommodate the drain-side injection mechanism. In particular, as can be seen from FIG. 5 of the patent, the program method utilizes a program current source circuitry 36a which includes a current source I.sub.s. Further, in order to program a memory cell to different program states (multiple bits-per-cell) the bandgap reference derived voltage BGR from a reference generator 134 must be selectively set to one of the target program-verify voltages (corresponding to each program state).
Accordingly, there has been developed by the inventor an improved unified program method and circuitry for use in Flash EEPROM memory cells which is relatively simple in its construction and consumes a small amount of power. The unified program method of the present invention requires only a single bandgap reference voltage and does not require the need of a current source. The present invention represent a significant improvement over the aforementioned '815 patent of the prior art.